High Speed CMOS VLSI Design Lecture 14 : Asynchronous Logic ( c ) 1997

Many styles of asynchronous circuits are mathematically fascinating, but practically useless. In particular, “delay insensitive” circuits which make no assumptions whatsoever about the relative delays of elements are generally useless because they involve tremendous overhead determining when logic has completed. We will avoid these types of circuits and focus on circuits which make a limited number of reasonable timing assumptions. In particular, we will look at three asynchronous design styles: static register-based micropipelines, simple asynchronous domino logic, and zero-overhead selftimed domino circuits.